1. Technical Field
Semiconductor devices containing a discontinuous cap layer are described herein. More particularly, semiconductor devices formed from substrates containing one or more conductive metal elements each having a cap material applied thereon as a discontinuous cap layer are described herein. Also described are methods for manufacturing such semiconductor devices.
2. Description of Related Art
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit. Integrated circuits can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that can be fabricated on a single silicon crystal semiconductor device, i.e., chip. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of the integrated circuits are increased. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip.
When fabricating integrated circuit wiring with a multi-layered scheme, an insulating or dielectric material, e.g., silicon oxide or the low dielectric constant insulators described herein, will normally be patterned with several thousand openings to create conductive line openings and/or via openings using photoprocessing techniques, e.g., photolithography with subsequent etching by a plasma process. These via openings are typically filled with a conductive metal material, e.g., aluminum, copper, etc., to interconnect the active and/or passive elements of the integrated circuits. The semiconductor device is then polished to level its surface.
A continuous cap layer is then normally deposited over the planarized surface featuring the dielectric material and conductive metal material. Next, a dielectric material is deposited over the continuous cap layer, via and conductive line openings are created within the dielectric layer as before, another conductive metal material is deposited within the openings and another continuous cap layer is deposited thereon. The process is then repeated to fabricate a multi-layer interconnect wiring system.
However, several problems exist when employing a continuous cap layer. First, the continuous cap layer possesses a relatively high dielectric constant, typically between 4 and 7, causing the resulting semiconductor device to also possess a relatively high effective dielectric constant, typically between 3 and 5. This, in turn, results in a higher capacitance between the conductive metal material causing the electric signals to travel at a slower speed with increased cross-talk through the interconnection wiring patterns. Second, the reliability of the semiconductor device is limited because the electromigration lifetime of the wiring structures is relatively short.
It would be desirable to provide a semiconductor device containing a discontinuous cap layer that can provide a relatively low effective dielectric constant for the device thereby allowing the electric signals to travel faster therethrough. This, in turn, will allow for the device to have a reduced effective capacitance. An increased electromigration lifetime of the device is also desirable.